Optoelectronic packages generally include one or more semiconductor dies, such as waveguide-based diode lasers, photo-detectors, and planar lightwave circuits (PLCs), permanently attached to a sub-mount. For optical alignment requirements, high precision is required during initial placement of a semiconductor die on a sub-mount. Generally, such high precision is achieved by aligning various alignment features, such as fiducial marks, on both the semiconductor die and the sub-mount by use of optical microscopy alignment method. Placement accuracy of instruments, such as optical microscopes, used in optical microscopy alignment methods depends on magnification level of the instruments. Higher magnification level of the instruments, such as optical microscope, leads to higher placement accuracy. This in turn increases the die placement time, thereby resulting in reduced process throughput, which is undesirable.
After placement, the semiconductor die is permanently attached to the sub-mount by way of soldering. Typically, the semiconductor dies used in optoelectronic packages have exposed optical facets. Therefore, for avoiding contamination of the optical facets by flux residue formed during soldering, fluxless soldering, such as eutectic soldering, is performed to attach the semiconductor die to the sub-mount. Solder materials with eutectic composition, such as gold-tin alloy, form hard solder joints with excellent creep resistance, thus optical alignment remains intact over time. However, solder materials having such eutectic composition cannot undergo subsequent reflow at eutectic temperature. Hence, semiconductor die attachment method using eutectic soldering is conventionally performed on singulated sub-mounts as shown in FIG. 1.
FIG. 1 is a cross-sectional view 100 that illustrates steps of a conventional method for semiconductor die attachment. A pre-singulated wafer 102 having a plurality of sub-mount pads 104 (hereinafter referred to as “sub-mount pads 104”) is loaded on a placement bench (not shown) of a dicing tool (not shown). The sub-mount pads 104 include first through third sub-mount pads 104A-104C. The pre-singulated wafer 102 including the first through third sub-mount pads 104A-104C may be formed by wafer processing, such as deposition, lithography, and etching, of an SiOB wafer (not shown). The first through third sub-mount pads 104A-104C are deposited with first through third solder layers 106A-106C having eutectic composition, such as gold-tin alloy. The first portion 102A along with the first sub-mount pad 104A and the first solder layer 106A constitutes a first sub-mount 108A of the pre-singulated wafer 102. Similarly, the second portion 102B along with the second sub-mount pad 104B and the second solder layer 106B constitutes a second sub-mount 108B, and the third portion 102C along with the third sub-mount pad 104C and the third solder layer 106C constitutes a third sub-mount 108C. The first through third sub-mounts 108A-108C are the first through third semiconductor die mounting sites of the pre-singulated wafer 102. The dicing tool dices the pre-singulated wafer 102 to singulate the first through third sub-mounts 108A-108C.
The diced first sub-mount 108A is then picked and loaded on a placement bench (not shown) of a die placement tool (not shown). The die placement tool uses optical microscopy alignment method for placing a semiconductor die 110 over the first sub-mount 108A. The semiconductor die 110 has a die pad 112 formed thereon. The die placement tool places the semiconductor die 110 over the first sub-mount 108A such that the die pad 112 comes in contact with the first solder layer 106A. For placing the semiconductor die 110 accurately, the die placement tool aligns a die alignment feature (not shown) of the semiconductor die 110 with a sub-mount alignment feature (not shown) of the first sub-mount 108A by using the optical microscopy alignment method. The die alignment feature and the sub-mount alignment feature are fiducial marks that are formed on the semiconductor die 110 and the first sub-mount 108A, respectively. The first sub-mount 108A is then reflowed at eutectic temperature, for example at 278° C., for permanently attaching the semiconductor die 110 to the first sub-mount 108A. The first solder layer 106A melts during the reflow process and solidifies when the reflow process ends, thereby permanently attaching the semiconductor die 110 to the first sub-mount 108A. The first sub-mount 108A having the semiconductor die 110 attached to it is a first die attached sub-mount package 114.
The entire process of die placement and reflow is then repeated for the remaining sub-mounts, such as the second and third sub-mounts 108B and 108C, to obtain second and third die attached sub-mount packages (not shown).
In the conventional method for semiconductor die attachment, the semiconductor die placement and reflow steps are performed for a single semiconductor die, such as the semiconductor die 110, at a time until each of the sub-mounts 108 has the semiconductor die 110 permanently attached to it. The time required for obtaining the first die attached sub-mount package 114 is a sum of wafer dicing time, die placement time, and reflow time. In one example, the wafer dicing time for obtaining one singulated sub-mount is 1 second, the die placement time is 3 seconds, and the reflow time is 25 seconds. Therefore, the time required for obtaining the first die attached sub-mount package 114 is 29 seconds. In a scenario, when the pre-singulated wafer 102 includes 1,000 sub-mounts similar to the first sub-mount 108A, the time required for obtaining 1,000 die attached sub-mount packages amounts to 29,000 seconds, i.e., 8.05 hours, which is very high and leads to reduced process throughput and low process efficiency.
Since cost of optoelectronic packaging depends, at least in part, on the process efficiency and process throughput of the semiconductor die attachment method, improvements in process efficiency and process throughput are highly desirable. In light of the foregoing, there exists a need for a semiconductor die attachment method that entails less placement time with high precision alignment accuracy, and has high process throughput with increased process efficiency in comparison to prior art solutions.